<!DOCTYPE html>

<html>
<head>
<meta charset="UTF-8">
<link href="style.css" type="text/css" rel="stylesheet">
<title>SQRTSD—Compute Square Root of Scalar Double-Precision Floating-Point Value </title></head>
<body>
<h1>SQRTSD—Compute Square Root of Scalar Double-Precision Floating-Point Value</h1>
<table>
<tr>
<th>Opcode/Instruction</th>
<th>Op /En</th>
<th>64/32 bit Mode Support</th>
<th>CPUID Feature Flag</th>
<th>Description</th></tr>
<tr>
<td>
<p>F2 0F 51/r</p>
<p>SQRTSD xmm1,xmm2/m64</p></td>
<td>RM</td>
<td>V/V</td>
<td>SSE2</td>
<td>Computes square root of the low double-precision floating-point value in xmm2/m64 and stores the results in xmm1.</td></tr>
<tr>
<td>
<p>VEX.NDS.128.F2.0F.WIG 51/r</p>
<p>VSQRTSD xmm1,xmm2, xmm3/m64</p></td>
<td>RVM</td>
<td>V/V</td>
<td>AVX</td>
<td>Computes square root of the low double-precision floating-point value in xmm3/m64 and stores the results in xmm1. Also, upper double-precision floating-point value (bits[127:64]) from xmm2 is copied to xmm1[127:64].</td></tr>
<tr>
<td>
<p>EVEX.NDS.LIG.F2.0F.W1 51/r</p>
<p>VSQRTSD xmm1 {k1}{z}, xmm2, xmm3/m64{er}</p></td>
<td>T1S</td>
<td>V/V</td>
<td>AVX512F</td>
<td>Computes square root of the low double-precision floating-point value in xmm3/m64 and stores the results in xmm1 under writemask k1. Also, upper double-precision floating-point value (bits[127:64]) from xmm2 is copied to xmm1[127:64].</td></tr></table>
<h3>Instruction Operand Encoding</h3>
<table>
<tr>
<td>Op/En</td>
<td>Operand 1</td>
<td>Operand 2</td>
<td>Operand 3</td>
<td>Operand 4</td></tr>
<tr>
<td>RM</td>
<td>ModRM:reg (w)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td>
<td>NA</td></tr>
<tr>
<td>RVM</td>
<td>ModRM:reg (w)</td>
<td>VEX.vvvv (r)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td></tr>
<tr>
<td>T1S</td>
<td>ModRM:reg (w)</td>
<td>EVEX.vvvv (r)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td></tr></table>
<p><strong>Description</strong></p>
<p>Computes the square root of the low double-precision floating-point value in the second source operand and stores the double-precision floating-point result in the destination operand. The second source operand can be an XMM register or a 64-bit memory location. The first source and destination operands are XMM registers.</p>
<p>128-bit Legacy SSE version: The first source operand and the destination operand are the same. The quadword at bits 127:64 of the destination operand remains unchanged. Bits (MAX_VL-1:64) of the corresponding destination register remain unchanged.</p>
<p>VEX.128 and EVEX encoded versions: Bits 127:64 of the destination operand are copied from the corresponding bits of the first source operand. Bits (MAX_VL-1:128) of the destination register are zeroed.</p>
<p>EVEX encoded version: The low quadword element of the destination operand is updated according to the writemask.</p>
<p>Software should ensure VSQRTSD is encoded with VEX.L=0. Encoding VSQRTSD with VEX.L=1 may encounter unpredictable behavior across different processor generations.</p>
<p><strong>Operation</strong></p>
<p><strong>VSQRTSD (EVEX encoded version)</strong></p>
<p>IF (EVEX.b = 1) AND (SRC2 *is register*)</p>
<p>THEN</p>
<p>SET_RM(EVEX.RC);</p>
<p>ELSE</p>
<p>SET_RM(MXCSR.RM);</p>
<p>FI;</p>
<p>IF k1[0] or *no writemask*</p>
<p>THEN</p>
<p>DEST[63:0] (cid:197) SQRT(SRC2[63:0])</p>
<p>ELSE</p>
<p>IF *merging-masking*</p>
<p>; merging-masking</p>
<p>THEN *DEST[63:0] remains unchanged*</p>
<p>ELSE</p>
<p>; zeroing-masking</p>
<p>THEN DEST[63:0] (cid:197) 0</p>
<p>FI;</p>
<p>FI;</p>
<p>DEST[127:64] (cid:197) SRC1[127:64]</p>
<p>DEST[MAX_VL-1:128] (cid:197) 0</p>
<p><strong>VSQRTSD (VEX.128 encoded version)</strong></p>
<p>DEST[63:0] (cid:197)SQRT(SRC2[63:0])</p>
<p>DEST[127:64] (cid:197)SRC1[127:64]</p>
<p>DEST[MAX_VL-1:128] (cid:197)0</p>
<p><strong>SQRTSD (128-bit Legacy SSE version)</strong></p>
<p>DEST[63:0] (cid:197)SQRT(SRC[63:0])</p>
<p>DEST[MAX_VL-1:64] (Unmodified)</p>
<p><strong>Intel C/C++ Compiler Intrinsic Equivalent</strong></p>
<p>VSQRTSD __m128d _mm_sqrt_round_sd(__m128d a, __m128d b, int r);</p>
<p>VSQRTSD __m128d _mm_mask_sqrt_round_sd(__m128d s, __mmask8 k, __m128d a, __m128d b, int r);</p>
<p>VSQRTSD __m128d _mm_maskz_sqrt_round_sd(__mmask8 k, __m128d a, __m128d b, int r);</p>
<p>SQRTSD __m128d _mm_sqrt_sd (__m128d a, __m128d b)</p>
<p><strong>SIMD Floating-Point Exceptions</strong></p>
<p>Invalid, Precision, Denormal</p>
<p><strong>Other Exceptions</strong></p>
<p>Non-EVEX-encoded instruction, see Exceptions Type 3.</p>
<p>EVEX-encoded instruction, see Exceptions Type E3.</p></body></html>